1. Field of the Invention
The present invention relates to a method for making a thin film transistor using a non-single-crystal silicon thin film suitable for driving elements of, for example, liquid crystal display devices, a liquid crystal display device and an electronic device using the same.
2. Related Art
Thin film transistors using thin films composed of non-single-crystal silicon thin films, such as amorphous silicon and polycrystalline silicon, have been intensively studied and developed. The technologies are expected to be used in various fields, for example, active matrix panels, which permit thin displays by the use of an inexpensive insulating substrate and inexpensive high-performance image sensors.
An example of conventional methods for making the thin film transistor will now be described with reference to FIG. 14. Thin film transistors are classified into two types, that is, a top-gate-type thin film transistor composed of an underlying silicon thin film forming source and drain regions and an overlying gate electrode, and a bottom-gate-type thin film transistor composed of an underlying gate electrode and an overlying silicon thin film. Herein, a top-gate-type thin film transistor is exemplified. The following manufacturing method is cited from "Fabrication of Self-Aligned Aluminum Gate Polysilicon Thin-Film Transistors Using Low-Temperature Crystallization Process", E. Ohno et al.; Jpn. J. Appl. Phys. Vol. 33 (1994), pp. 635-638.
As shown in FIG. 14(a), after a SiO.sub.2 buffer layer 2 is formed on a glass substrate 1, an amorphous silicon layer 3 having a thickness of 100 nm is formed thereon by a low-pressure chemical vapor deposition (LPCVD) process. The amorphous silicon layer 3 is annealed in a nitrogen atmosphere at 600.degree. C. for 24 hours. Next, as shown in FIG. 14(b), after patterning the amorphous silicon layer 3, a SiO.sub.2 gate insulating film 4 having a thickness of 100 nm is formed by a atmospheric pressure CVD process and is annealed at 600.degree. C. for 12 hours.
Next, as shown in FIG. 14(c), an aluminum (Al) film is formed by a sputtering process and patterned to form a gate electrode 5. Phosphorus or boron is implanted using the gate electrode 5 as a mask to form source and drain regions 6 in the silicon layer 3. Because protons are simultaneously implanted, no annealing is required. Next, as shown in FIG. 14(d), a SiO.sub.2 insulating interlevel film 7 is formed by a tetraethoxysilane plasma enhanced CVD (hereinafter referred to as "TEOS-PECVD") process, contact holes 8, 8 are formed in the interlevel film 7, and an aluminum film 9 is finally deposited and formed as an electrode.
The thin film transistor manufactured by the above-mentioned steps is used as a driving element, for example, for a liquid crystal display device for a long period, hence it is important to reduce change in electrical characteristics with time as much as possible and to ensure sufficient reliability. In conventional manufacturing processes of thin film transistors, however, correlations between various parameters in production and reliability of devices have not been clarified, and a manufacturing process with high reliability has not been investigated.
The manufacturing steps (environment and processing atmospheres) and devices must be isolated from moisture in order to ensure reliability as much as possible, however, spin-on-glass films (hereinafter referred to as SOG films) often used as interlevel films for planarization in semiconductor devices have a disadvantage of high moisture absorption. Japanese Patent Laid-Open No. 4-93049 discloses removal of moisture in the SOG film by nitrogen annealing at approximately 430.degree. C. after coating of an SOG film. Further, Japanese Patent Laid-Open No. 4-164351 discloses removal of moisture in an SOG film by annealing, for example, at 400.degree. C. for 30 minutes after the formation of a plasma oxide film on the SOG film.
On the other hand, it has been reported that when a thin film transistor provided with a SiO.sub.2 gate insulating film by a PECVD process is annealed at approximately 270.degree. C. in a moist atmosphere, the interface state density between the SiO.sub.2 film and the polycrystalline silicon film decreases and thus the threshold voltage (hereinafter referred to as Vth) of the thin film transistor is reduced ("High Quality SiO.sub.2 /Si Interfaces of Poly-Crystalline Silicon Thin Film Transistors by Annealing in Wet atmosphere", N. Sano et al.; IEEE ELECTRON DEVICE LETTERS, VOL. 16, NO. 5, MAY 1955). According to another report, wet oxygen annealing (moisture-containing oxygen annealing) after deposition of a TEOS-O.sub.3 NSG film modifies the film quality into a nonhygroscopic state ("Effect of Low-Temperature Annealing on Hygroscopicity of TEOS-O.sub.3 Atmospheric CVD NSG Film", Oda et al.; Semiconductor World, February 1993).
Although these reports refer to the control of the Vth and the improvement in the moisture resistance by employing annealing in moist environments (hereinafter referred to as wet annealing), these do not clarify the correlation between the wet annealing and the reliability of the device, and thus these technologies do not improve the reliability of thin film transistors.